1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more particularly, it relates to the structure of a nonvolatile semiconductor memory device capable of storing information of at least four values (information of at least two bits) in a single memory cell. More specifically, the present invention relates to the structure of an electrically reloadable nonvolatile semiconductor memory device such as a flash memory, for example.
2. Description of the Prior Art
In order to meet increase of the storage capacity of a nonvolatile semiconductor memory device such as a flash memory, a structure capable of storing multivalued data exceeding binary data in a single memory cell has been developed.
FIG. 118 is a schematic block diagram showing the overall structure of a conventional AND flash memory 8000.
A memory cell array 100 includes a number of memory cells having floating gates and control gates. Referring to FIG. 118, the memory cell array 100 is divided into two memory cell blocks 100R and 100L.
The control gates, drains and sources of the memory cells are connected to word lines WL, bit lines BL and source lines SCL (not shown) respectively.
FIG. 118 representatively shows a single word line WL and a single bit line BL. Row decoders 110 selectively drive the word lines WL on the basis of externally supplied address signals. A sense latch circuit 120 is provided on single ends of the bit lines BL. The bit lines BL are selected on the basis of selection signals output from column decoders 130, for transferring read data and write data.
The sense latch circuit 120 includes a column switching circuit (not shown in FIG. 118) for selecting the bit lines BL on the basis of the selection signals from the column decoders 130.
An address buffer 140 supplies the address signals to the column decoders 130 and the row decoders 110.
A chip control part 200 externally receives an access control signal (not shown) and a clock signal (not shown) and entirely controls the internal circuits of the flash memory 8000 for write control and read control of the memory cells. The chip control part 200 controls a power supply generation part 150 thereby switching operating voltages of word drivers (not shown) driving the potentials of the word lines WL in response to operation modes for erasing, writing, reading and the like.
Data latch circuits DL-L and DL-R are data buffers temporarily holding data transferred in data write and read operations.
The operation modes of the flash memory 8000 are not particularly restricted but instructed by an access control signal externally supplied to the chip control part 200 or command data supplied through a data bus or the like, and include data rewrite (erase and write) and data read modes.
In the conventional AND four-valued flash memory 8000 shown in FIG. 118, each memory cell is in an information storage state selected from an erased state, a first write state, a second write state and a third write state. The four information storage states in total correspond to states decided by 2-bit data. In other words, each memory cell can store 2-bit data.
Therefore, the flash memory 8000 sets three different types of write verify voltages applied to the word lines WL in the write operation and sequentially switches the voltages for performing write operations three times.
In each write operation, the chip control part 200 controls an operation of writing two-valued (1-bit) write data “0” or “1” (“L” or “H”) held in a sense latch SL (included in the sense latch circuit 120) connected with a memory cell subjected to writing while setting the corresponding write verify voltage every write operation. Information of four values (two bits) can be written in a single memory cell due to this structure, as described later in detail.
The flash memory 8000 sets three types of voltages as word line selection levels applied by the word line WL in the read operations and captures data of two values (one bit) read from the memory cell in the three read operations through the sense latch circuit 120, and the chip control part 200 converts the data to information of four values (two bits) after termination of the three read operations.
The outlines of write and read operations are now described.
In the write operation, a data string of two values (one bit) to be written and address signals are captured in the address buffer/data input/output buffer 140 from a data input/output terminal group 10 and an address signal input terminal group 12 respectively.
The chip control circuit 200 separates the data string of two values (one bit) to be written into data strings of upper and lower bit data (or data strings of odd and even bit data) and transfers the data strings to the data latches (hereinafter referred to as non-selected selection latches) DL-L and DL-R connected with non-selected memory cells in the memory cell array 100 through signal lines 20 respectively for temporarily latching the data strings.
The chip control part 200 captures the data held in the data latches DL-L and DL-R through the signal lines 20 when performing each of “write 1 (write operation for obtaining the first write state)”, “write 2 (write operation for obtaining the second write state)” and “write 3 (write operation for obtaining the third write state)” and converts the data to data “0” or “1” of two values (one bit) corresponding to the data of four values (two bits) to be written in the selected memory cell in response to “write 1”, “write 2” and “write 3”. Further, the chip control part 200 transfers the converted data to the sense latch SL in the sense latch circuit 120 connected with the selected memory cell through a signal line 18 so that the aforementioned write operations “write 1”, “write 2” and “write 3” are performed in accordance with the binary data latched in the selected sense latch SL.
Thus, information of four values (two bits) can be written in a single memory cell by temporarily holding binary data separated into an upper bit string and a lower bit string in the data latches DL-L and DL-R, forming write data of two values (one bit) for each of three write operations (“write 1” to “write 3”) having different verify voltages and performing the three write operations having different verify voltages.
In the read operation, three different types of voltages are sequentially applied to the selected word line WL so that information “0” or “1” of two values (one bit) read from the memory cell of the memory cell array 100 to the selected sense latch SL by three read operations is transferred to and temporarily held in the data latches DL-L and DL-R. Three types of data “0” or “1” of two values (one bit) in the data strings read through the three read operations, held in the data latches DL-L and DL-R and latched in the selected sense latch SL are transferred to the chip control circuit 200 through the signal lines 18 and 20.
The chip control circuit 200 composites upper and lower bits of data of four values (two bits) on the basis of the data transferred in the aforementioned manner. The chip control circuit 200 outputs the composited upper and lower bits from the data input/output terminal group 10 through the data input/output buffer 140.
The aforementioned write and read operations are now described in further detail.
[Conventional Write Operation of Four-Valued Data]
FIG. 119 illustrates the relation between write data and thresholds of memory cell transistors in a conventional two-valued AND flash memory. In the write and read operations, data are written and read with reference to a determination level Vj01.
FIG. 120 illustrates the relation between write data and thresholds of memory cell transistors in the conventional four-valued AND flash memory 8000. In the write and read operations, data are written and read with reference to three determination levels Vj1, Vj2 and Vj3.
As hereinabove described, the conventional four-valued AND flash memory 8000 divides the threshold into four types after writing as shown in FIG. 120, while the conventional two-valued AND flash memory divides the threshold (Vth) of the memory cell transistor into two types “0” and “1” after writing.
Therefore, the flash memory 8000 requires three types of determination levels Vj1, Vj2 and Vj3 for determining the respective levels.
FIGS. 121 to 126 are conceptual diagrams showing data held in the data latches DL-L and DL-R and the sense latch SL and thresholds of memory cells after writing in first to third processing steps of the write operation.
FIG. 121 shows data held in the latches DL-L, DL-R and SL in the first processing step of the write operation, and FIG. 122 shows thresholds of the memory cells in the first processing step of the write operation.
FIG. 123 shows data held in the latches DL-L, DL-R and SL in the second processing step of the write operation, and FIG. 124 shows thresholds of the memory cells in the second processing step of the write operation.
FIG. 125 shows data held in the latches DL-L, DL-R and SL in the third processing step of the write operation, and FIG. 126 shows thresholds of the memory cells in the third processing step of the write operation.
Before starting the write operation, the thresholds of the memory cells are set below the determination level Vj1.
Referring to FIGS. 121 and 122, data DQ0 to DQ3 and DQ4 to DQ7 are stored in the data latches DL-R and DL-L respectively among data DQ0 to DQ7 for one byte input from terminals I/O0 to I/O7 included in the data input/output terminal group 10 in the first step of the write operation. Referring to FIG. 121, it is assumed that C9h represents the input 1-byte data in hexadecimal notation.
The data latch DL-R latches the input data DQ0 to DQ3 from the terminals I/O0 to I/O3 and the data latch DL-L latches the input data DQ4 to DQ7 from the terminals I/O4 to I/O7 as for the entire sector (data corresponding to one word line WL).
In the following description, consider each 2-bit data (DQ4, DQ0), (DQ5, DQ1), (DQ6, DQ2) and (DQ7, DQ3), having one of the data DQ4 to DQ7 held in the data latch DL-L as the upper bit and one of the data DQ0 to DQ3 held in the data latch DL-R as the lower bit, as a set of data.
The chip control part 200 operates the aforementioned sets of data included in the data latches DL-R and DL-L and zeros only bit data of the sense latch SL corresponding to such data that the upper bit held in the data latch DL-L is “0” and the lower bit held in the data latch DL-R is “1”.
As shown in FIG. 121, the sense latch SL holds “0111” from the high-order position. On the basis of the data thus held in the sense latch SL, data are written in memory cells MC1 to MC4 corresponding to the bits of the sense latch SL respectively. The memory cells MC1 to MC4 are connected with the same word line WL. The third determination level Vj3 is employed as the determination value for a verify operation.
At this time, data is written in the memory cell corresponding to the data “0” in the sense latch SL. Thus, the data (corresponding to data “01”) of level 4 is written in the memory cell MC4 corresponding to the most significant bit of the sense latch SL.
In practice, a high voltage is applied to the word line WL thereby writing the data through an FN (Fowler-Nordheim) tunnel current.
A voltage below the word line voltage is applied to bit lines BL corresponding to the bit data “1” of the sense latch SL, in order to relax the voltage applied from the word line WL. Consequently, data is written in only the memory cell connected with the bit line BL corresponding to the bit data “0” held in the sense latch SL.
Referring to FIGS. 123 and 124, the data held in the data latches DL-R and DL-L are operated in the second step of the write operation for writing “0” in the bit of the sense latch SL corresponding to such a set of data that the upper bit held in the data latch DL-L is “0” and the lower bit held in the data latch DL-R is “0”. The determination value in the verify operation is changed to Vj2, and data are written only in the memory cells connected with bit lines BL corresponding to the data DQ5 and DQ1 in data writing.
Referring to FIGS. 125 and 126, the data held in the data latches DL-R and DL-L are operated in the third step of the write operation for writing “0” in the bit of the sense latch SL corresponding to such a set of data that the upper bit held in the data latch DL-L is “1” and the lower bit held in the data latch DL-R is “0”. The determination value in the verify operation is changed to Vj1, and data are written only in the memory cells connected with bit lines BL corresponding to the data DQ6 and DQ2 in data writing.
After inputting all data to be written, the write operation is terminated through three operations and write processing as described above.
[Conventional Read Operation of Four-Valued Data]
The read operation is now described.
FIGS. 127 to 132 are conceptual diagrams showing data held in the data latches DL-L and DL-R and the sense latch SL, thresholds of memory cells and determination levels in first to third processing steps of the read operation.
FIG. 127 shows data held in the latches DL-L, DL-R and SL in the first processing step of the read operation, and FIG. 128 shows thresholds of the memory cells and determination levels in the first processing step of the read operation.
FIG. 128 shows data held in the latches DL-L, DL-R and SL in the second processing step of the read operation, and FIG. 129 shows threshold of the memory cells and determination levels in the second processing step of the read operation.
FIG. 129 shows data held in the latches DL-L, DL-R and SL in the second processing step of the read operation, and FIG. 130 shows thresholds of the memory cells and determination levels in the second processing step of the read operation.
FIG. 131 shows data held in the latches DL-L, DL-R and SL in the third processing step of the read operation, and FIG. 132 shows thresholds of the memory cells and determination levels in the third processing step of the read operation.
Referring to FIGS. 127 and 128, data are read at the first determination level Vj1 and the results are stored in the sense latch SL in the first processing step of the read operation. The data are transferred to the data latch DL-R, and the sense latch SL is cleared.
Referring to FIGS. 129 and 130, data are read at the second determination level Vj2 and the results are stored in the sense latch SL in the second processing step of the read operation. The data are transferred to the data latch DL-L and the sense latch SL is cleared again.
Referring to FIGS. 131 and 132, data are finally read at the third determination level Vj3 and the results are stored in the sense latch SL in the third processing step of the read operation. The chip control circuit 200 sets the data of the data latch DL-R to “1” only on such a bit position that both of the data stored in the sense latch SL and the data in the data latch DL-R are “0”.
The data latches DL-L and DL-R sequentially output the data DQ4 to DQ7 and DQ0 to DQ3 respectively.
Also in the read operation, the data are output after all three read operations are defined.
For example, Japanese Patent Laying-Open No. 9-297996 (1997) discloses a more detailed structure of such a multivalued memory. This memory also requires a plurality of processing steps in each of read and write operations, similarly to the aforementioned multivalued memory.
In the conventional AND four-valued flash memory 8000, as hereinabove described, the speed of the chip for read and write operations is deteriorated by a delay following a plurality of processing steps, as compared with the general two-valued flash memory. This problem of deterioration of the speed gets serious as the number of values is increased.